Summary of the course:
Digital circuits are traditionally designed using specialized hardware description languages like VHDL and Verilog in the Register Transfer Level (RTL). The increasing complexity of today digital systems requires more efficient and flexible design methodologies. High Level Synthesis (HLS) methods are an active research area since 1980s and finally matured to use in industrial applications. Unlike traditional VHDL based design flows the input of a HLS synthesis system is a standard ANSI C/C++ description and the structure of the synthesized architecture can be defined using compiler directives. By changing the directives less design effort and much shorter time is required to generate several different architectures for the same algorithm. Area, speed, power dissipation, memory bandwidth parameters of the different solutions can be compared during design space exploration and the best one can be selected for a particular implementation.
The aim of the course is to give an insight to modern HLS design methodologies and systems. Students will gain experience in designing, simulating, and optimizing of algorithms and creating digital circuits using HLS system.
Michael Fingeroff, “High-Level Synthesis Blue Book”, Xlibris, 2010
Philippe Coussy, Adam Morawiec, “High-Level Synthesis: from Algorithm to Digital Circuit”, Springer, 2008
Louise Crockett, Ross Elliot, Martin Enderwitz, Bob Stewart, David Northcote, “The Zynq Book Tutorials for Zybo and ZedBoard”, Strathclyde Academic Media, 2015
Xilinx Vivado Design Suite User Guide: High-Level Synthesis
Xilinx Vivado Design Suite Tutorial: High-Level Synthesis
Raul Camposano and Wayne Wolf, eds., “High-Level VLSI Synthesis”, Springer, 1991.
Sumit Gupta, Rajesh Gupta, Nikil D. Dutt, Alexandru Nicolau, “SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits”, Springer, 2004.
Additional lecturers, if exist (name, position, degree): Dr. András Kiss, senior lecturer, PhD